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[AArch64] Adjust comparison constant if adjusting it means less instructions #151024

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Merged
merged 4 commits into from
Aug 18, 2025
Merged

[AArch64] Adjust comparison constant if adjusting it means less instructions #151024

merged 4 commits into from
Aug 18, 2025

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AZero13
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@AZero13 AZero13 commented Jul 28, 2025

Prefer constants that require less instructions to materialize, in both Global-ISel and Selection-DAG

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llvmbot commented Jul 28, 2025

@llvm/pr-subscribers-backend-aarch64

Author: AZero13 (AZero13)

Changes

Prefer constants that require less instructions to materialize, in both Global-ISel and Selection-DAG

Patch is 34.24 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/151024.diff

6 Files Affected:

  • (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+29-18)
  • (modified) llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp (+2-2)
  • (modified) llvm/test/CodeGen/AArch64/icmp-cst.ll (+221-506)
  • (modified) llvm/test/CodeGen/AArch64/srem-seteq.ll (+4-6)
  • (modified) llvm/test/CodeGen/AArch64/urem-seteq-optsize.ll (+2-3)
  • (modified) llvm/test/CodeGen/AArch64/urem-seteq.ll (+2-3)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 7b49754ee7e1f..bdb14c2303f5e 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -3486,6 +3486,13 @@ bool isLegalCmpImmed(APInt C) {
   return isLegalArithImmed(C.abs().getZExtValue());
 }
 
+unsigned numberOfInstrToLoadImm(APInt C) {
+  uint64_t Imm = C.getZExtValue();
+  SmallVector<AArch64_IMM::ImmInsnModel> Insn;
+  AArch64_IMM::expandMOVImm(Imm, 32, Insn);
+  return Insn.size();
+}
+
 static bool isSafeSignedCMN(SDValue Op, SelectionDAG &DAG) {
   // 0 - INT_MIN sign wraps, so no signed wrap means cmn is safe.
   if (Op->getFlags().hasNoSignedWrap())
@@ -3955,6 +3962,7 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
       // CC has already been adjusted.
       RHS = DAG.getConstant(0, DL, VT);
     } else if (!isLegalCmpImmed(C)) {
+      unsigned NumImmForC = numberOfInstrToLoadImm(C);
       // Constant does not fit, try adjusting it by one?
       switch (CC) {
       default:
@@ -3963,42 +3971,45 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
       case ISD::SETGE:
         if (!C.isMinSignedValue()) {
           APInt CMinusOne = C - 1;
-          if (isLegalCmpImmed(CMinusOne)) {
+          if (isLegalCmpImmed(CMinusOne) ||
+              (NumImmForC > numberOfInstrToLoadImm(CMinusOne))) {
             CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
             RHS = DAG.getConstant(CMinusOne, DL, VT);
           }
         }
         break;
       case ISD::SETULT:
-      case ISD::SETUGE:
-        if (!C.isZero()) {
-          APInt CMinusOne = C - 1;
-          if (isLegalCmpImmed(CMinusOne)) {
-            CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
-            RHS = DAG.getConstant(CMinusOne, DL, VT);
-          }
+      case ISD::SETUGE: {
+        // C is not 0 because it is a legal immediate.
+        APInt CMinusOne = C - 1;
+        if (isLegalCmpImmed(CMinusOne) ||
+            (NumImmForC > numberOfInstrToLoadImm(CMinusOne))) {
+          CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
+          RHS = DAG.getConstant(CMinusOne, DL, VT);
         }
-        break;
+      } break;
       case ISD::SETLE:
       case ISD::SETGT:
         if (!C.isMaxSignedValue()) {
           APInt CPlusOne = C + 1;
-          if (isLegalCmpImmed(CPlusOne)) {
+          if (isLegalCmpImmed(CPlusOne) ||
+              (NumImmForC > numberOfInstrToLoadImm(CPlusOne))) {
             CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
             RHS = DAG.getConstant(CPlusOne, DL, VT);
           }
         }
         break;
       case ISD::SETULE:
-      case ISD::SETUGT:
-        if (!C.isAllOnes()) {
-          APInt CPlusOne = C + 1;
-          if (isLegalCmpImmed(CPlusOne)) {
-            CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
-            RHS = DAG.getConstant(CPlusOne, DL, VT);
-          }
+      case ISD::SETUGT: {
+        // The maxmimum possible number, -1, is a legal cmp immediate, so no
+        // need to check for it.
+        APInt CPlusOne = C + 1;
+        if (isLegalCmpImmed(CPlusOne) ||
+            (NumImmForC > numberOfInstrToLoadImm(CPlusOne))) {
+          CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
+          RHS = DAG.getConstant(CPlusOne, DL, VT);
         }
-        break;
+      } break;
       }
     }
   }
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index 3ba08c8c1d988..9b604f2fca46e 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -659,10 +659,10 @@ tryAdjustICmpImmAndPred(Register RHS, CmpInst::Predicate P,
   auto IsMaterializableInSingleInstruction = [=](uint64_t Imm) {
     SmallVector<AArch64_IMM::ImmInsnModel> Insn;
     AArch64_IMM::expandMOVImm(Imm, 32, Insn);
-    return Insn.size() == 1;
+    return Insn.size();
   };
 
-  if (!IsMaterializableInSingleInstruction(OriginalC) &&
+  if (IsMaterializableInSingleInstruction(OriginalC) >
       IsMaterializableInSingleInstruction(C))
     return {{C, P}};
 
diff --git a/llvm/test/CodeGen/AArch64/icmp-cst.ll b/llvm/test/CodeGen/AArch64/icmp-cst.ll
index b6f452bb42cec..b49da44920db0 100644
--- a/llvm/test/CodeGen/AArch64/icmp-cst.ll
+++ b/llvm/test/CodeGen/AArch64/icmp-cst.ll
@@ -1,687 +1,402 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -mtriple=aarch64-linux-gnu -global-isel=0 < %s | FileCheck %s --check-prefix=CHECK-SD
-; RUN: llc -mtriple=aarch64-linux-gnu -global-isel=1 < %s | FileCheck %s --check-prefix=CHECK-GI
+; RUN: llc -mtriple=aarch64-linux-gnu -global-isel=0 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=aarch64-linux-gnu -global-isel=1 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
 define i1 @ule_11111111(i32 noundef %in) {
-; CHECK-SD-LABEL: ule_11111111:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    mov w8, #4370 // =0x1112
-; CHECK-SD-NEXT:    movk w8, #4369, lsl #16
-; CHECK-SD-NEXT:    cmp w0, w8
-; CHECK-SD-NEXT:    cset w0, lo
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: ule_11111111:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w8, #286331153 // =0x11111111
-; CHECK-GI-NEXT:    cmp w0, w8
-; CHECK-GI-NEXT:    cset w0, ls
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: ule_11111111:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #286331153 // =0x11111111
+; CHECK-NEXT:    cmp w0, w8
+; CHECK-NEXT:    cset w0, ls
+; CHECK-NEXT:    ret
   %out = icmp ult i32 %in, 286331154
   ret i1 %out
 }
 
 define i1 @ule_22222222(i32 noundef %in) {
-; CHECK-SD-LABEL: ule_22222222:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    mov w8, #8739 // =0x2223
-; CHECK-SD-NEXT:    movk w8, #8738, lsl #16
-; CHECK-SD-NEXT:    cmp w0, w8
-; CHECK-SD-NEXT:    cset w0, lo
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: ule_22222222:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w8, #572662306 // =0x22222222
-; CHECK-GI-NEXT:    cmp w0, w8
-; CHECK-GI-NEXT:    cset w0, ls
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: ule_22222222:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #572662306 // =0x22222222
+; CHECK-NEXT:    cmp w0, w8
+; CHECK-NEXT:    cset w0, ls
+; CHECK-NEXT:    ret
   %out = icmp ult i32 %in, 572662307
   ret i1 %out
 }
 
 define i1 @ule_33333333(i32 noundef %in) {
-; CHECK-SD-LABEL: ule_33333333:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    mov w8, #13108 // =0x3334
-; CHECK-SD-NEXT:    movk w8, #13107, lsl #16
-; CHECK-SD-NEXT:    cmp w0, w8
-; CHECK-SD-NEXT:    cset w0, lo
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: ule_33333333:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w8, #858993459 // =0x33333333
-; CHECK-GI-NEXT:    cmp w0, w8
-; CHECK-GI-NEXT:    cset w0, ls
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: ule_33333333:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #858993459 // =0x33333333
+; CHECK-NEXT:    cmp w0, w8
+; CHECK-NEXT:    cset w0, ls
+; CHECK-NEXT:    ret
   %out = icmp ult i32 %in, 858993460
   ret i1 %out
 }
 
 define i1 @ule_44444444(i32 noundef %in) {
-; CHECK-SD-LABEL: ule_44444444:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    mov w8, #17477 // =0x4445
-; CHECK-SD-NEXT:    movk w8, #17476, lsl #16
-; CHECK-SD-NEXT:    cmp w0, w8
-; CHECK-SD-NEXT:    cset w0, lo
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: ule_44444444:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w8, #1145324612 // =0x44444444
-; CHECK-GI-NEXT:    cmp w0, w8
-; CHECK-GI-NEXT:    cset w0, ls
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: ule_44444444:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #1145324612 // =0x44444444
+; CHECK-NEXT:    cmp w0, w8
+; CHECK-NEXT:    cset w0, ls
+; CHECK-NEXT:    ret
   %out = icmp ult i32 %in, 1145324613
   ret i1 %out
 }
 
 define i1 @ule_55555555(i32 noundef %in) {
-; CHECK-SD-LABEL: ule_55555555:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    mov w8, #21846 // =0x5556
-; CHECK-SD-NEXT:    movk w8, #21845, lsl #16
-; CHECK-SD-NEXT:    cmp w0, w8
-; CHECK-SD-NEXT:    cset w0, lo
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: ule_55555555:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w8, #1431655765 // =0x55555555
-; CHECK-GI-NEXT:    cmp w0, w8
-; CHECK-GI-NEXT:    cset w0, ls
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: ule_55555555:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #1431655765 // =0x55555555
+; CHECK-NEXT:    cmp w0, w8
+; CHECK-NEXT:    cset w0, ls
+; CHECK-NEXT:    ret
   %out = icmp ult i32 %in, 1431655766
   ret i1 %out
 }
 
 define i1 @ule_66666666(i32 noundef %in) {
-; CHECK-SD-LABEL: ule_66666666:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    mov w8, #26215 // =0x6667
-; CHECK-SD-NEXT:    movk w8, #26214, lsl #16
-; CHECK-SD-NEXT:    cmp w0, w8
-; CHECK-SD-NEXT:    cset w0, lo
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: ule_66666666:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w8, #1717986918 // =0x66666666
-; CHECK-GI-NEXT:    cmp w0, w8
-; CHECK-GI-NEXT:    cset w0, ls
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: ule_66666666:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #1717986918 // =0x66666666
+; CHECK-NEXT:    cmp w0, w8
+; CHECK-NEXT:    cset w0, ls
+; CHECK-NEXT:    ret
   %out = icmp ult i32 %in, 1717986919
   ret i1 %out
 }
 
 define i1 @ule_77777777(i32 noundef %in) {
-; CHECK-SD-LABEL: ule_77777777:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    mov w8, #30584 // =0x7778
-; CHECK-SD-NEXT:    movk w8, #30583, lsl #16
-; CHECK-SD-NEXT:    cmp w0, w8
-; CHECK-SD-NEXT:    cset w0, lo
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: ule_77777777:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w8, #2004318071 // =0x77777777
-; CHECK-GI-NEXT:    cmp w0, w8
-; CHECK-GI-NEXT:    cset w0, ls
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: ule_77777777:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #2004318071 // =0x77777777
+; CHECK-NEXT:    cmp w0, w8
+; CHECK-NEXT:    cset w0, ls
+; CHECK-NEXT:    ret
   %out = icmp ult i32 %in, 2004318072
   ret i1 %out
 }
 
 define i1 @ule_88888888(i32 noundef %in) {
-; CHECK-SD-LABEL: ule_88888888:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    mov w8, #34953 // =0x8889
-; CHECK-SD-NEXT:    movk w8, #34952, lsl #16
-; CHECK-SD-NEXT:    cmp w0, w8
-; CHECK-SD-NEXT:    cset w0, lo
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: ule_88888888:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w8, #-2004318072 // =0x88888888
-; CHECK-GI-NEXT:    cmp w0, w8
-; CHECK-GI-NEXT:    cset w0, ls
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: ule_88888888:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #-2004318072 // =0x88888888
+; CHECK-NEXT:    cmp w0, w8
+; CHECK-NEXT:    cset w0, ls
+; CHECK-NEXT:    ret
   %out = icmp ult i32 %in, -2004318071
   ret i1 %out
 }
 
 define i1 @ule_99999999(i32 noundef %in) {
-; CHECK-SD-LABEL: ule_99999999:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    mov w8, #39322 // =0x999a
-; CHECK-SD-NEXT:    movk w8, #39321, lsl #16
-; CHECK-SD-NEXT:    cmp w0, w8
-; CHECK-SD-NEXT:    cset w0, lo
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: ule_99999999:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w8, #-1717986919 // =0x99999999
-; CHECK-GI-NEXT:    cmp w0, w8
-; CHECK-GI-NEXT:    cset w0, ls
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: ule_99999999:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #-1717986919 // =0x99999999
+; CHECK-NEXT:    cmp w0, w8
+; CHECK-NEXT:    cset w0, ls
+; CHECK-NEXT:    ret
   %out = icmp ult i32 %in, -1717986918
   ret i1 %out
 }
 
 define i1 @uge_11111111(i32 noundef %in) {
-; CHECK-SD-LABEL: uge_11111111:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    mov w8, #4368 // =0x1110
-; CHECK-SD-NEXT:    movk w8, #4369, lsl #16
-; CHECK-SD-NEXT:    cmp w0, w8
-; CHECK-SD-NEXT:    cset w0, hi
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: uge_11111111:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w8, #286331153 // =0x11111111
-; CHECK-GI-NEXT:    cmp w0, w8
-; CHECK-GI-NEXT:    cset w0, hs
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: uge_11111111:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #286331153 // =0x11111111
+; CHECK-NEXT:    cmp w0, w8
+; CHECK-NEXT:    cset w0, hs
+; CHECK-NEXT:    ret
   %out = icmp ugt i32 %in, 286331152
   ret i1 %out
 }
 
 define i1 @uge_22222222(i32 noundef %in) {
-; CHECK-SD-LABEL: uge_22222222:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    mov w8, #8737 // =0x2221
-; CHECK-SD-NEXT:    movk w8, #8738, lsl #16
-; CHECK-SD-NEXT:    cmp w0, w8
-; CHECK-SD-NEXT:    cset w0, hi
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: uge_22222222:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w8, #572662306 // =0x22222222
-; CHECK-GI-NEXT:    cmp w0, w8
-; CHECK-GI-NEXT:    cset w0, hs
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: uge_22222222:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #572662306 // =0x22222222
+; CHECK-NEXT:    cmp w0, w8
+; CHECK-NEXT:    cset w0, hs
+; CHECK-NEXT:    ret
   %out = icmp ugt i32 %in, 572662305
   ret i1 %out
 }
 
 define i1 @uge_33333333(i32 noundef %in) {
-; CHECK-SD-LABEL: uge_33333333:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    mov w8, #13106 // =0x3332
-; CHECK-SD-NEXT:    movk w8, #13107, lsl #16
-; CHECK-SD-NEXT:    cmp w0, w8
-; CHECK-SD-NEXT:    cset w0, hi
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: uge_33333333:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w8, #858993459 // =0x33333333
-; CHECK-GI-NEXT:    cmp w0, w8
-; CHECK-GI-NEXT:    cset w0, hs
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: uge_33333333:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #858993459 // =0x33333333
+; CHECK-NEXT:    cmp w0, w8
+; CHECK-NEXT:    cset w0, hs
+; CHECK-NEXT:    ret
   %out = icmp ugt i32 %in, 858993458
   ret i1 %out
 }
 
 define i1 @uge_44444444(i32 noundef %in) {
-; CHECK-SD-LABEL: uge_44444444:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    mov w8, #17475 // =0x4443
-; CHECK-SD-NEXT:    movk w8, #17476, lsl #16
-; CHECK-SD-NEXT:    cmp w0, w8
-; CHECK-SD-NEXT:    cset w0, hi
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: uge_44444444:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w8, #1145324612 // =0x44444444
-; CHECK-GI-NEXT:    cmp w0, w8
-; CHECK-GI-NEXT:    cset w0, hs
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: uge_44444444:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #1145324612 // =0x44444444
+; CHECK-NEXT:    cmp w0, w8
+; CHECK-NEXT:    cset w0, hs
+; CHECK-NEXT:    ret
   %out = icmp ugt i32 %in, 1145324611
   ret i1 %out
 }
 
 define i1 @uge_55555555(i32 noundef %in) {
-; CHECK-SD-LABEL: uge_55555555:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    mov w8, #21844 // =0x5554
-; CHECK-SD-NEXT:    movk w8, #21845, lsl #16
-; CHECK-SD-NEXT:    cmp w0, w8
-; CHECK-SD-NEXT:    cset w0, hi
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: uge_55555555:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w8, #1431655765 // =0x55555555
-; CHECK-GI-NEXT:    cmp w0, w8
-; CHECK-GI-NEXT:    cset w0, hs
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: uge_55555555:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #1431655765 // =0x55555555
+; CHECK-NEXT:    cmp w0, w8
+; CHECK-NEXT:    cset w0, hs
+; CHECK-NEXT:    ret
   %out = icmp ugt i32 %in, 1431655764
   ret i1 %out
 }
 
 define i1 @uge_66666666(i32 noundef %in) {
-; CHECK-SD-LABEL: uge_66666666:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    mov w8, #26213 // =0x6665
-; CHECK-SD-NEXT:    movk w8, #26214, lsl #16
-; CHECK-SD-NEXT:    cmp w0, w8
-; CHECK-SD-NEXT:    cset w0, hi
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: uge_66666666:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w8, #1717986918 // =0x66666666
-; CHECK-GI-NEXT:    cmp w0, w8
-; CHECK-GI-NEXT:    cset w0, hs
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: uge_66666666:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #1717986918 // =0x66666666
+; CHECK-NEXT:    cmp w0, w8
+; CHECK-NEXT:    cset w0, hs
+; CHECK-NEXT:    ret
   %out = icmp ugt i32 %in, 1717986917
   ret i1 %out
 }
 
 define i1 @uge_77777777(i32 noundef %in) {
-; CHECK-SD-LABEL: uge_77777777:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    mov w8, #30582 // =0x7776
-; CHECK-SD-NEXT:    movk w8, #30583, lsl #16
-; CHECK-SD-NEXT:    cmp w0, w8
-; CHECK-SD-NEXT:    cset w0, hi
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: uge_77777777:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w8, #2004318071 // =0x77777777
-; CHECK-GI-NEXT:    cmp w0, w8
-; CHECK-GI-NEXT:    cset w0, hs
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: uge_77777777:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #2004318071 // =0x77777777
+; CHECK-NEXT:    cmp w0, w8
+; CHECK-NEXT:    cset w0, hs
+; CHECK-NEXT:    ret
   %out = icmp ugt i32 %in, 2004318070
   ret i1 %out
 }
 
 define i1 @uge_88888888(i32 noundef %in) {
-; CHECK-SD-LABEL: uge_88888888:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    mov w8, #34951 // =0x8887
-; CHECK-SD-NEXT:    movk w8, #34952, lsl #16
-; CHECK-SD-NEXT:    cmp w0, w8
-; CHECK-SD-NEXT:    cset w0, hi
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: uge_88888888:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w8, #-2004318072 // =0x88888888
-; CHECK-GI-NEXT:    cmp w0, w8
-; CHECK-GI-NEXT:    cset w0, hs
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: uge_88888888:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #-2004318072 // =0x88888888
+; CHECK-NEXT:    cmp w0, w8
+; CHECK-NEXT:    cset w0, hs
+; CHECK-NEXT:    ret
   %out = icmp ugt i32 %in, -2004318073
   ret i1 %out
 }
 
 define i1 @uge_99999999(i32 noundef %in) {
-; CHECK-SD-LABEL: uge_99999999:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    mov w8, #39320 // =0x9998
-; CHECK-SD-NEXT:    movk w8, #39321, lsl #16
-; CHECK-SD-NEXT:    cmp w0, w8
-; CHECK-SD-NEXT:    cset w0, hi
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: uge_99999999:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w8, #-1717986919 // =0x99999999
-; CHECK-GI-NEXT:    cmp w0, w8
-; CHECK-GI-NEXT:    cset w0, hs
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: uge_99999999:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #-1717986919 // =0x99999999
+; CHECK-NEXT:    cmp w0, w8
+; CHECK-NEXT:    cset w0, hs
+; CHECK-NEXT:    ret
   %out = icmp ugt i32 %in, -1717986920
   ret i1 %out
 }
 
 define i1 @sle_11111111(i32 noundef %in) {
-; CHECK-SD-LABEL: sle_11111111:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    mov w8, #4370 // =0x1112
-; CHECK-SD-NEXT:    movk w8, #4369, lsl #16
-; CHECK-SD-NEXT:    cmp w0, w8
-; CHECK-SD-NEXT:    cset w0, lt
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: sle_11111111:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w8, #286331153 // =0x11111111
-; CHECK-GI-NEXT:    cmp w0, w8
-; CHECK-GI-NEXT:    cset w0, le
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: sle_11111111:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #286331153 // =0x11111111
+; CHECK-NEXT:    cmp w0, w8
+; CHECK-NEXT:    cset w0, le
+; CHECK-NEXT:    ret
   %out = icmp slt i32 %in, 286331154
   ret i1 %out
 }
 
 define i1 @sle_22222222(i32 noundef %in) {
-; CHECK-SD-LABEL: sle_22222222:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    mov w8, #8739 // =0x2223
-; CHECK-SD-NEXT:    movk w8, #8738, lsl #16
-; CHECK-SD-NEXT:    cmp w0, w8
-; CHECK-SD-NEXT:    cset w0, lt
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: sle_22222222:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w8, #572662306 // =0x22222222
-; CHECK-GI-NEXT:    cmp w0, w8
-; CHECK-GI-NEXT:    cset w0, le
-; CHECK-GI-NEXT:    ret
+; CHECK-LABEL: sle_22222222:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #572662306 // =0x22222222
+; CHECK-NEXT:    cmp w0, w8
+; CHECK-NEXT:    cset w0, le
+; CHECK-NEXT:    ret
   %out = icmp slt i32 %in, 572662307
   ret i1 %out
 }
 
 define i1 @sle_33333333(i32 noundef %in) {
-; CHECK-SD-LABEL: sle_33333333:
-; CHECK-SD:       // %bb.0:
-; CHECK-SD-NEXT:    mov w8, #13108 // =0x3334
-; CHECK-SD-NEXT:    movk w8, #13107, lsl #16
-; CHECK-SD-NEXT:    cmp w0, w8
-; CHECK-SD-NEXT:    cset w0, lt
-; CHECK-SD-NEXT:    ret
-;
-; CHECK-GI-LABEL: sle_33333333:
-; CHECK-GI:       // %bb.0:
-; CHECK-GI-NEXT:    mov w8, #858993459 // =0x33333333
-; CHECK-GI-NEXT:    cmp w0, w8
-; CHECK-GI-NEXT:    cset w0,...
[truncated]

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AZero13 commented Aug 7, 2025

@davemgreen Thoughts on this?

davemgreen
davemgreen reviewed Aug 11, 2025
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[AArch64] Adjust comparison constant if adjusting it means less instr…
5fa2318 
…uctions

Prefer constants that require less instructions to materialize, in both Global-ISel and Selection-DAG
@AZero13 AZero13 requested a review from davemgreen August 11, 2025 18:29
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AZero13 commented Aug 14, 2025

@davemgreen Fixed!

davemgreen
davemgreen approved these changes Aug 18, 2025
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Thanks. LGTM.

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AZero13 commented Aug 18, 2025

Thank you. @davemgreen can we please merge

@davemgreen davemgreen merged commit 0e52092 into llvm:main Aug 18, 2025
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@AZero13 AZero13 deleted the immediates branch August 18, 2025 14:27
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MacDue commented Aug 18, 2025

Looks like this is failing on the buildbots: https://lab.llvm.org/buildbot/#/builders/51/builds/21763 shows a "should not be -1 here!" assertion.

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AZero13 commented Aug 18, 2025

#154124

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AZero13 commented Aug 18, 2025

Looks like this is failing on the buildbots: https://lab.llvm.org/buildbot/#/builders/51/builds/21763 shows a "should not be -1 here!" assertion.

#154124

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AZero13 commented Aug 18, 2025

Fixed

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@davemgreen davemgreen davemgreen approved these changes

@nasherm nasherm Awaiting requested review from nasherm

@efriedma-quic efriedma-quic Awaiting requested review from efriedma-quic

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